`include "./macro.vh" 
module test_top(
    input  wire        I_osc_clk,
    
    // //edp in
    // output wire        DP_rx_hpd,
    
    // output wire [0 :0] O_DP0_dp159_OE,
    // inout  wire        B_DP0_dp159_iic_scl_io,
    // inout  wire        B_DP0_dp159_iic_sda_io,
    // inout  wire        B_DP0_aux_rx_io_n,//dp in
    // inout  wire        B_DP0_aux_rx_io_p,
    // input  wire        I_DP0_mgtrefclk1_pad_n,
    // input  wire        I_DP0_mgtrefclk1_pad_p,
    // input  wire [03:0] I_DP0_lnk_rx_lane_n,
    // input  wire [03:0] I_DP0_lnk_rx_lane_p,

    // output wire        O_DP1_dp159_rst,
    // inout  wire        B_DP1_dp159_iic_scl,
    // inout  wire        B_DP1_dp159_iic_sda,
    // inout  wire        B_DP1_aux_rx_io_n,
    // inout  wire        B_DP1_aux_rx_io_p,
    // input  wire        I_DP1_mgtrefclk1_n,
    // input  wire        I_DP1_mgtrefclk1_p,
    
    // //edp out
    // input  wire        DP_tx_hpd,
    
    // output wire        O_dp130_nRst,
    // inout  wire        iic_main_scl_io,
    // inout  wire        iic_main_sda_io,
    // inout  wire        B_DP0_aux_tx_io_n,
    // inout  wire        B_DP0_aux_tx_io_p,
    // input  wire        I_DP0_mgtrefclk0_pad_n,
    // input  wire        I_DP0_mgtrefclk0_pad_p,
    // output wire [03:0] O_DP0_phy_txn_out,
    // output wire [03:0] O_DP0_phy_txp_out,

    // output wire        O_dp130_nRst_0,
    // inout  wire        IIC_0_sda_io,
    // inout  wire        IIC_0_scl_io,
    // inout  wire        aux_tx_io_n_0,
    // inout  wire        aux_tx_io_p_0,
    // input  wire        I_DP1_mgtrefclk0_n,
    // input  wire        I_DP1_mgtrefclk0_p,
    // input  wire [03:0] I_DP1_phy_rxn,
    // input  wire [03:0] I_DP1_phy_rxp,
    // output wire [03:0] phy_txn_out_0,
    // output wire [03:0] phy_txp_out_0,
    
    
    
    output wire    [3:0]   O_oe_out        ,
    output wire    [3:0]   O_load_out      ,
    output wire    [3:0]   O_clock_out     ,
    output wire    [4:0]   O_scan1_out     ,
    output wire    [4:0]   O_scan2_out     ,
    output wire    [4:0]   O_scan3_out     ,
    output wire    [4:0]   O_scan4_out     ,
    output wire    [23:0]  O_data_out     
    // output wire            O_deghost_ctrl  ;
);

wire            set_clk     ; 
wire            set_d_ok    ;
wire  [23:0]    set_addr    ;
wire  [7:0]     set_data    ;

//背光数据
wire            we_t;
// wire            we_end_t;
reg             we_end_t;
wire   [12:0]   waddr_t;
wire   [15:0]   wdata_t;


wire rst_n;
wire sclk;
wire clk_100m;
wire clk_200m;

wire rx_clk;
// wire set_clk;
// assign set_clk = sclk_100m;

assign set_clk = sclk;
assign rx_clk  = sclk;

localparam  CNT_FOR_FPS_60  = 1_000_000_000/(8*60);
reg [23:0]      cnt;
reg             vs      ;

reg             ram_wsel;
reg             ram_rsel;

wire    [15:0]  pixel_data_i    ;

wire    [3:0]   mode            ;

wire    [5:0]   burst_row       ;
wire    [6:0]   burst_col       ;
wire            pixel_en        ;
wire    [15:0]  pixel_data      ;


wire            ram_rden        ;
wire    [12:0]  ram_raddr       ;
wire    [15:0]  ram_rdata       ;

wire    [7:0]   x               ;
wire    [7:0]   y               ;

wire    [8:0]   cfg_win_col_num ;
wire    [8:0]   cfg_win_row_num ;

pll_out_0 pll_out
 (
  .clk_out1     (clk_100m),
  .clk_out2     (clk_200m),
  .clk_out3     (sclk),
  .locked       (rst_n),
  .clk_in1      (I_osc_clk)
 );
 
always@(posedge sclk)begin
    if(!rst_n)
        cnt <= 'd0 ;
    else if(cnt=='d0)
        cnt <= CNT_FOR_FPS_60;
    else 
        cnt <= cnt -1;
end
always@(posedge sclk)begin
    if(!rst_n)
        vs <= 'd0 ;
    else if(cnt== CNT_FOR_FPS_60 - 'd2)
        vs <= 'd1;
    else 
        vs <= 'd0;
end
 
        

data_pattern data_pattern(
    // system signal
    .I_sclk                 (sclk       ),  // 125M
    .I_rst_n                (rst_n      ),
    .I_cfg_win_col_num      (cfg_win_col_num     ),   // 带载列数（宽度）
    .I_cfg_win_row_num      (cfg_win_row_num      ),   // 带载行数（高度）
    // input  frame
    .I_frame_start          (vs         ),
    
    .I_pixel_data           (pixel_data_i),
    
    .I_mode                 (mode       ),
    .I_x                    (x          ),
    .I_y                    (y          ),
    // output frame
    .O_burst_row            (burst_row   ),
    .O_burst_col            (burst_col   ),
    .O_pixel_en             (pixel_en    ),
    .O_pixel_data           (pixel_data  )
);
`ifdef ILA_DEBUG
ila_data_pattern ila_data_pattern(
        .clk        (sclk                ),              
        .probe0     (vs                  ),
        .probe1     (burst_row           ),
        .probe2     (burst_col           ),
        .probe3     (pixel_en            ),
        .probe4     (pixel_data          )
);
`endif
wire            oe_out        ;
wire            load_out      ;
wire    [4:0]   scan_out      ;
wire            clock_out     ;
wire    [5:0]   data_out      ;
wire            deghost_ctrl  ;



assign  O_oe_out        = {4{oe_out}        };
assign  O_load_out      = {4{load_out}      };
assign  O_clock_out     = {4{clock_out}     };
assign  O_scan1_out     = scan_out          ;
assign  O_scan2_out     = scan_out          ;
assign  O_scan3_out     = scan_out          ;
assign  O_scan4_out     = scan_out          ;
assign  O_data_out[5:0]     = data_out          ;
assign  O_data_out[11:6]    = data_out          ;
assign  O_data_out[17:12]   = data_out          ;
assign  O_data_out[23:18]   = data_out          ;



assign  we_t        = pixel_en  ;
// assign  we_end_t    = 'd0 ;
assign  waddr_t     = { burst_row[5:0] , burst_col[6:0]} ;
assign  wdata_t     = pixel_data;

always@(posedge sclk)begin
    if(!rst_n)
        we_end_t <= 'd0 ;
    else if(cnt== 'd20)
        we_end_t <= 'd1;
    else 
        we_end_t <= 'd0;
end

display_top
#(
.DW (   6   )
)
display_top(
    .I_sclk             (sclk           ),
    .I_rst_n            (rst_n          ),
    

    .vs                 (vs             ),
    
    
     //bl_data
    .BL_clk             (sclk           ),
    .BL_we              (we_t           ), 
    .BL_waddr           (waddr_t        ), 
    .BL_wdata           (wdata_t        ),
    .BL_we_end          (we_end_t       ),
    .lock               (1'd0           ), //(lock           ),

    // scan output
    .O_scan_out         (scan_out       ),

    // led signal
    .O_oe_out           (oe_out         ),
    .O_load_out         (load_out       ),
    .O_clock_out        (clock_out      ),
    .O_data_out         (data_out       ),
    .O_vsync_out        (               ),
    .O_en               (               ),
    .O_scan_con         (               ),
    .O_tcon_12v_con     (               ),


    .set_clk            (set_clk        ),
    .set_d_ok           (set_d_ok       ),
    .set_addr           (set_addr       ),
    .set_data           (set_data       ),


    .tout               (               )
    );
    
assign      set_clk  = sclk;
assign      set_d_ok = 'd0;
assign      set_addr = 'd0;
assign      set_data = 'd0;

`ifdef VIO_DEBUG
vio_0 vio_0_inst (
      .clk(sclk),              
      // ,.probe_in0(),    
      // ,.probe_in1(),
      .probe_out0(pixel_data_i  ),
      .probe_out1(mode          ),
      .probe_out2(x             ),
      .probe_out3(y             ),

    .probe_out4   (cfg_win_col_num     ),
    .probe_out5   (cfg_win_row_num     )

   );
`else
assign pixel_data_i  =  16'h3fff    ;
assign mode          =  'd1         ;
assign x             =  'd0         ;
assign y             =  'd0         ;
assign cfg_win_col_num =  'd128     ;
assign cfg_win_row_num =  'd64      ;
`endif
endmodule